1. Field of the Invention
The disclosure relates to a method of exposing a semiconductor wafer and an exposure apparatus for semiconductor wafer.
Priority is claimed on Japanese Patent Application No. 2010-111170, filed May 13, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, with the increase in the diameter of semiconductor wafers in the semiconductor manufacturing process, in order to reduce the cost of the lithographic exposure process used to form resist patterns, there has been an increase in the shot surface area. However, because of the reduction of the DOF (depth of focus) and adoption of micropatterns, there tends to be defocusing, making it difficult to achieve high manufacturing yield. This defocusing refers to the out-of-focus condition (defocusing) during lithographic exposure, caused by unwanted matter on the rear surface of the wafer mainly in the semiconductor manufacturing process, accompanied by a reduction in the planarity of the surface of the wafer.
In the lithographic exposure process step, if the above-mentioned type of defocused portion occurs on the surface of the semiconductor wafer, it is not possible to form a normal resist pattern, and subsequently there is a risk of forming abnormalities in, for example, an interconnect pattern formed using the resist pattern. For example, if an abnormal resist pattern is used to form a system of interconnects (interconnect pattern), the interconnects can become thinned and peel, and this can affect even normal chips in the surrounding area. Also, if an abnormal resist pattern is used to form holes, the hole diameter could increase and may result in such effects as the sinking of the interlayer film in subsequent process steps.
In the case of patterning a photoresist film on a wafer using lithographic projection exposure, the wafer is generally placed onto a stage and the height is measured over the entire surface of the wafer, using an autofocus sensor. Then, based on the results of the height measurements, the focus is adjusted during the exposure processing, and exposure processing is performed while controlling the stage or the like, so that the surface of the wafer is as parallel as possible with the exposure apparatus. These are disclosed in Japanese Patent Application Publications Nos. JP-A 10-270317 and JP-A 1-264220.
The exposure method and exposure apparatus described in Japanese Patent Application Publications Nos. JP-A 10-270317 and JP-A 1-264220 are configured so that a defocused portion occurring as the result of unwanted matter as mentioned above can be detected by an autofocus scan. According to Japanese Patent Application Publication No. JP-A 10-270317, by issuing an alarm when a defocused portion is detected on the wafer, it is possible to prevent exposure processing from proceeding at that point. According to Japanese Patent Application Publication No. JP-A 1-264220, when a defocused portion is detected on the wafer, the exposure in the direction of movement is stopped, and exposure is performed in the direction that is reversed from the direction of movement, so that there is no poor resolution within the region on the substrate.
In the method and apparatus of Japanese Patent Application Publications Nos. JP-A 10-270317 and JP-A 1-264220, however, if a defocused portion is detected on the wafer, either an alarm is issued to prompt an operator to stop the exposure processing or the exposure processing direction is reversed. For this reason, in Japanese Patent Application Publications Nos. JP-A 10-270317 and JP-A 1-264220, similar to the case described above, it is not possible to form a normal resist pattern at the defocused portions on the wafer, and abnormal interconnect patterns or holes are formed, and this can affect even surrounding normal chips. Also, with the art of Japanese Patent Application Publications Nos. JP-A 10-270317 and JP-A 1-264220, stopping the exposure processing or reversing the processing direction reduces the semiconductor wafer productivity.
In the related art, including that of Japanese Patent Application Publications Nos. JP-A 10-270317 and JP-A 1-264220, as shown in FIG. 10A and FIG. 10B, the autofocus processing is first performed to measure the planarity of the wafer surface and detect defocused portions, and then the exposure scan processing is performed. The scanning is performed in a Y-direction. The exposure position P50 corresponds to the slit. On the surface 201 of the wafer 200, however, between each of the autofocus beams 101 disposed in a direction perpendicular to the scan direction, it is not possible to accurately measure the planarity of the surface 201 of the wafer 200, so that there is a risk, for example, of the detection missing a defocused portion.
Even if the movement of the stage is, for example, compensated at the time of the exposure processing at a part in which there is abnormal planarity on the wafer surface, it is difficult to compensate other than for linear components. For this reason, even if the above-described autofocus scanning is performed and the stage movement is compensated based on information regarding a detected defocused portion, positions occur at which it is not possible to perform localized adjustment of the focus on the wafer surface, the beam becoming defocused at such positions, making it impossible to form a normal pattern.
For this reason, with the method of the related art, in the case in which there is a partial abnormality in the planarity on the wafer surface, an abnormal pattern remains at this position and is allowed to proceed to the subsequent etching process step. The part of the wafer surface with the pattern abnormality was etched as is, this affecting other normal chips downstream in the manufacturing process.